The pipelining is a technique of decomposing a sequential process into sub operations, with each sub process being executed in a special dedicated segment that operate concurrently with all the segments.
A pipeline can be visualized a collection of processing segments through which binary information flows.
The pipeline concept is organized into two areas
1) Arithmetic pipeline
2) Instruction pipeline
An arithmetic pipeline divides an arithmetic operation into sub operations for execution in the pipeline segments.
An instruction pipeline operates on s stream of instructions by overlapping the fetch, decode, execute and store phase of the instruction cycle.
In a pipelined processor, a pipeline has two ends, the input end and the output end. Between these ends, there are multiple stages/segments such that output of one stage is connected to input of next stage and each stage performs a specific operation.
Interface registers are used to hold the intermediate output between two stages. These interface registers are also called latch or buffer.
All the stages in the pipeline along with the interface registers are controlled by a common clock.
The simplest instruction pipeline breaks instruction processing into two parts: a fetch stage S1 and an execute stage S2 .Thus a 2-stage pipeline increases throughput by overlapping instruction fetching and instruction execution.